| | 数字上变频器和下变频器的IC型号、厂商、供应商、PDF资料： | |
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| IC型号 | 厂商 | PDF资料下载 | 供应商 | 说明 |
| AD9853 | ADI | | 查找供应商 |
| Master fclk |
165MHz |
| Resolution (Bits) |
10bit |
| Pwr Supply (V) |
3.1 to 5.25 |
| I Supply total (max) |
230mA |
| FS Iout (mA nom) |
10mA |
| Compliance Range (V) |
1V |
| REFCLK Multiplier |
Yes | |
| AD6654 | ADI |  下载 | 查找供应商 |
- Integrated 14-Bit , 92.16 MSPS ADC
- IF Sampling Frequencies to 200 MHz
- Internal 2.4 V Reference, 2.2 Vp-p Analog Input Range
- Internal Differential Track & Hold Analog Input
- Processes 4/6 Wideband Carriers Simultaneously
- Fractional Clock Multiplier to 200 MHz
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- Programmable Decimating FIR Filters,
Interpolating Half Band
- Filters and Programmable AGC
Loops with 96dB range
- Three 16-bit Configurable Parallel
Output Ports
- User Configurable Built in Self Test
(BIST) Capability
- 8/16-bit Microport and Sport/SPI
Serial Port Control | |
| AD6652 | ADI | | 查找供应商 |
- SNR = 90 dB in 150 kHz bandwidth (to Nyquist @ 61.44 MSPS
- Worst harmonic = 83 dBc (to Nyquist @ 61.44 MSPS)
- Integrated dual-channel ADC:
- Sample rates up to 65 MSPS
- IF sampling frequencies to 200 MHz
- Internal ADC voltage reference
- Integrated ADC sample and-hold inputs
- Flexible analog input range (1 V to 2 V p-p)
- Differential analog inputs
- ADC clock duty cycle stabilizer
- 85 dB channel isolation/crosstalk |
- Integrated wideband digital downconverter (DDC):
- Crossbar switched DDC inputs
- Digital resampling for noninteger decimation
- Programmable decimating FIR filters
- Flexible control for multicarrier and phased array
- Dual AGC stages for output level control
- Dual 16-bit parallel or 8-bit link output ports
- User-configurable built-in self-test (BIST) capability
- Energy-saving power-down modes | |
| AD6633 | ADI | | 查找供应商 |
- 4 or 6 wideband digital upconverter channels
- VersaCREST™ crest reduction engine reduces demands on external power amplifiers
- One 20-bit complex input port (I/Q interleaved), shared among 4 or 6 processing channels
- Two 18-bit output ports for parallel I and Q, or interleaved I and Q on a single port
- All-pass phase equalizer filters (meets cdma2000 requirements)
- Programmable RAM coefficient FIR filters (RCF) with resampling
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- FIR interpolating filters and Fifth-order interpolating CIC filter
- Full complex NCO, 32-bit tuning resolution (fine), worst spur better than - 105 dBc
- Complex FIR filter for frequency equalization
- Power monitoring and output Automatic Gain Control
- 16-bit/8-bit MicroPort or SPI/SPORT compatible serial port
- 3.3 V I/O and 1.8 V core supplies
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| AD6623 | ADI | | 查找供应商 |
- RAM Coefficient Filter (RCF)
- Programmable IF And Modulation For Each Channel
- Programmable Interpolating RAM Coefficient Filter
- p/4 DQPSK Differential Phase Encoder
- 3p/8 8-PSK Linear Encoder
- 8-PSK Linear Encoder
- Programmable GMSK Look-Up-Table
- Programmable QPSK Look-Up-Table
- All-Pass Phase Equalizer
- Programmable Fine Scalar
- Programmable Power Ramp Unit |
- 18-Bit Parallel Digital IF Output
- 18-Bit Bi-Directional Parallel Digital
IF Input/Output
Allows Cascade Of Chips For Additional Channels
- Four Independent Digital Transmitters
In Single Package
- Digital Re-Sampling For Non-Integer
Decimation Rates | |
| AD6622 | ADI | | 查找供应商 |
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- 65 MSPS Wideband Input and Output (18-Bit)
- Four Independent Digital Transmitters in a Single Package
- Separate 3-Wire Serial Data Input for Each Channel
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- Programmable Interpolating
RAM Coefficient Filters
- Programmable IF For Each Channel
- JTAG Boundary Scan
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| AD6636 | ADI | 下载 | 查找供应商 |
- Six Independent Wideband Processing Channels
- Processes 6 Wideband carriers (UMTS, CDMA2000, TD-SCDMA, etc.)
- Four Single Ended or Two LVDS Parallel Input Ports (16 linear bit plus 3-bit exponent) at 150 MHz
- Can support 300MHz input using some external interface logic
- Three 16-bit Parallel Output Ports operating at
up to 200 MHz
- Real or complex input ports
- Quadrature correction andDC correction
for complex inputs |
- Can support output rate up to 34 MSPS
- RMS/Peak Power monitoring of
input ports
- Programmable attenuator control for
external Digital Variable Gain
Amplifier (DVGA)
- Three Programmable coefficient FIR
Filters per channel
- One Interpolating Half Band
Filter per channel | |
| AD6635 | ADI | | 查找供应商 |
- 80 MSPS Wide Band Inputs (14 linear
bit plus 3 RSSI)
- Processes 4 WCDMA channels (UMTS or cdma2000 1x)
or 8 GSM/EDGE, IS136 Channels
- Eight Independent Digital Receivers
in a Single Package
- Four 16-Bit Parallel Output Ports and
Four 8-Bit Link Ports
- Programmable Digital AGC Loops with
96d B Range
- Digital Re-sampling for non-Integer
Decimation Rates |
- Programmable Decimating FIR Filters
- Four Interpolating Half Band Filters
- Programmable Attenuator Control for
Clip Prevention and External Gain
Ranging via Level Indicator
- Flexible Control for Multi-Carrier
and Phased Array
- 3.3 Volt I/O, 2.5 Volt CMOS Core
- User Configurable Built in Self Test
(BIST) Capability | |
| AD6634 | ADI | | 查找供应商 |
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- 80 MSPS Wide Band Inputs (14 Linear Bit Plus 3 RSSI)
- Two WCDMA-Digital Receivers In Single Package
- 16-Bit Parallel Outputs
- Digital AGC Output Bits for RAKE Receiver
- Digital Re-Sampling For Non-Integer Decimation Rates
- Programmable Decimating FIR Filters
- Flexible Control For Multi-Carrier And Phased Array
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- Programmable Attenuator Control
for Clip Prevention And External Gain
Ranging Via Level Indicator
- 3.3 Volt I/O, 2.5 Volt CMOS Core
- User Configurable Built In Self Test
(BIST) Capability
- JTAG Boundary Scan
- 156 pin BGA Package
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| AD6624A | ADI | | 查找供应商 |
- 100 MSPS Wideband Input (14-Bit)
- Four Independent Digital Receivers in a Single Package
- Digital Re-sampling for non-Integer Decimation Rates
- 3.3 Volt CMOS
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- Programmable Decimating RAM Coefficient FIR Filters
- JTAG Boundary Scan, Built in Self Test (BIST) Capability
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